The present invention relates to a semiconductor device and a method for fabricating the same. More particularly, the present invention relates to a semiconductor device having a capacitor and a method for fabricating the same.
Recently, semiconductor technologies have been developed to combine a logic device with a memory device. The logic device, such as a central processing unit (CPU), may have information processing functions, while the memory device may be used to store the information before and/or after being processed. Further, in addition to the combination of the logic device and the memory device, an analog device and a radio frequency (RF) device may also be combined.
In an integrated circuit (IC), various semiconductor devices, such as a transistor, a capacitor, and a resistor, may be integrated onto a single chip. In addition, various methods for effectively fabricating the semiconductor devices have been developed. For example, an analog capacitor used in a logic circuit, such as a complementary metal-oxide-semiconductor (CMOS) logic circuit, may be formed to have a Polysilicon/Insulator/Polysilicon (PIP) structure or a Metal/Insulator/Metal (MIM) structure.
The analog capacitor having the PIP structure may prevent noise generated from the logic circuit and modulate the signals in the logic circuit. In addition, the analog capacitor may include a bottom electrode and a top electrode, both being fabricated by a polysilicon material, which is identical to the material constituting a gate electrode of a logic transistor of the logic circuit. Accordingly, the analog capacitor can be fabricated simultaneously with the gate electrode without additional processes.
FIG. 1 is a sectional view illustrating a semiconductor device including the analog capacitor having the PIP structure and the logic circuit according to the related art. In one embodiment, a region ‘A’ may represent a resistor region, a region ‘B’ may represent a capacitor region, and a region ‘C’ may represent a logic transistor region.
As shown in FIG. 1, an isolation layer 3, which may be used to define active regions, is formed on a semiconductor substrate 1. Semiconductor substrate 1 may comprise silicon.
A resistor 7 may be formed in region ‘A’ of semiconductor substrate 1. In addition, a bottom electrode 9, a dielectric layer 13, and a top electrode 15 may be formed in region ‘B’ of semiconductor substrate 1 to form the analog capacitor of the PIP structure. Further, a gate electrode 11, source/drain regions 10 formed in semiconductor substrate 1 adjacent to gate electrode 11, and a gate insulating layer 5 interposed between gate electrode 11 and source/drain regions 10 may be formed in region ‘C,’ thereby form a metal-oxide-semiconductor (MOS) transistor.
A first interlayer dielectric layer 17 is formed on semiconductor substrate 1 covering resistor 7, the analog capacitor, and the MOS transistor. Then, a second interlayer dielectric layer 19 is formed on first interlayer dielectric layer 17. In addition, contact plugs 21, 23, and 25 are formed in first interlayer dielectric layer 17 and second interlayer dielectric layer 19 to electrically contact top electrode 15 of the analog capacitor, and gate electrode 11 and source/drain regions 10 of the MOS transistor. In one embodiment, contact plugs 21, 23, and 25 may comprise metal.
In the semiconductor device having the above structure, the capacitance of the analog capacitor may be determined according to an area of dielectric layer 13 interposed between bottom electrode 9 and top electrode 15.
To form the analog capacitor, a photo process and an etching process may be performed on a first polysilicon layer, an oxide-nitride-oxide (ONO) layer, and a second polysilicon layer formed on semiconductor substrate 1. However, residues may remain after the performance of the photo process and the etching process. Thus, an over-etching process may be performed to remove the residues. At this time, the polysilicon layer formed in region ‘C,’ on which the photo process and the etching process are also performed, may have a thickness smaller than the target thickness of the polysilicon layer formed in region ‘C’ due to the over-etching process.
That is, the photo process and the etching process performed to the second polysilicon layer and the ONO layer may have a negative influence on subsequent etching processes performed to the first polysilicon layer.
Since an etch rate of the first polysilicon layer varies according to particular portions of the first polysilicon layer, on which an etching processing is performed, the problem occurred in the etching process performed to the second polysilicon layer may continue to occur in the etching process performed to the first polysilicon layer.
Meanwhile, the first polysilicon layer may be used to form a gate electrode of the CMOS transistor in other regions. Accordingly, to form the analog capacitor, the etching process may be performed more than once, such that the gate electrode may have a thickness smaller than its target thickness. Therefore, the electrical properties of the semiconductor device may be changed due to the reduced thickness of the gate electrode, thereby lowering the reliability of the semiconductor device.